Various semiconductor failure modes necessitate a wide variety of testing tools to find out what's wrong.  It's ironic that sometimes a malfunctioning device can be the single most important tool for understanding what's wrong with our systems and be the catalyst for ensuring that future ones work properly. Yet this happens all the time and because of the various semiconductor failure modes, we have a large number of tests which can tell us what went wrong. In this article, we look at some of the ways an integrated circuit can fail and what it means when an error is found. We also look at the important difference between non destructive testing and destructive testing.

Semiconductor Failure Modes are important tools which help in the design of robust integrated circuits.  Designing a semiconductor chip that has a low probability of failure is a daunting task. Given the large number of electronic components, the sensitivity of the materials to contamination and the required precision of manufacturing, it's hardly surprising that chips fail every now and then. What's astonishing is that so many of them keep working as designed for so long. It's truly a testament to our consistency and meticulousness.

But these robust and precise designs don't come about merely due to hard work. What's important is the process for the chip design which pools the experience of all the various engineers who have expertise in the field. In fact, there's a structured way of going about chip design called Failure Mode and Effects Analysis (FMEA.) In this article, we learn about semiconductor failure modes, how they're identified and addressed.

Analyzing printed circuit board failures and finding out which techniques to use to detect them is a challenging task.

Printed Circuit Boards (PCBs) are complicated systems. They have many different facets and subsystems which are getting tinier every year as technology advances. So small in fact, that we're quickly running up against theoretical limits on how much further we can take them. This complexity leaves them susceptible to a host of defects and in this article, we take a look at a few printed circuit board failures and what types of failure analysis techniques are available for each of them.

As Integrated Circuits (ICs) become smaller and smaller, we're bumping up against practical and theoretical limitations on the number of electronic components we can cram into a space. For example, at low enough levels, quantum tunnelling effects render insulation far less effective. Another major problem is heat management. Every circuit generates heat and when we have a large density of circuits, we have to dissipate the heat as quickly as possible. This calls for careful design which becomes more and more complicated as the semiconductor chips grow smaller. Too much heat and it can significantly decrease the longevity of the components. In order to design more efficient heat dissipation layouts and analyze the flaws in existing chips, we need microthermal imaging techniques to tell give us a "heat map." Fluorescent imaging is one of the most important techniques which can help us.

In a complex semiconductor, finding out the causes of a problem can get very complicated. Even after a problem has been analyzed, we don't always get to the root cause even when we detect why a certain error has occurred. This way, it's possible to conduct many detection tests on an integrated circuit with each test revealing yet another cause which in turn must be examined further. One example of such a process is the detection of current leakage. Current leakage is the cause of many frustrating errors in a semiconductor which manifest themselves in bizarre ways. It's also very difficult to detect because of the millions of components on a single chip.

But even when we find the actual leakage, we must work to understand why it is happening and what error is causing it. In this article, we examine how we detect current leakage by measuring the infinitesimally small amount of excess heat generated due to it.

Given the fact that the first priority of a failure analysis testing team is to try and ensure that the sample isn't damaged, it's nor surprising that x-ray imaging is a very important testing technique used to detect problems in integrated circuits. The unique feature of this technique is that it gives us a way to get really detailed information about the insides of a chip in a way that many other techniques cannot - even though methods such as acoustic microscopy can also probe beneath the surface in a non destructive manner.

All manufacturing companies must undergo regular independent auditing to determine compliance with various statutes. One of these is a directive regarding the presence of hazardous substances in the final product and it's absolutely essential for a manufacturer of semiconductors and electronic components to have the proper certifications in this regard. In this article, we look at the Restriction of Hazardous Substances (RoHS) directive and what it means to be in compliance with it.

Interestingly, directives regulating hazardous substances are the strongest in the European Union. In fact, the RoHS was adopted only in the EU in 2003. It goes hand in hand with other directives such as the Waste Electrical and Electronic Equipment Directive (WEEE).

Though it is the goal of all semiconductor failure analysts to preserve the chip when determining the cause of failure, in many cases this isn't possible. Sometimes the problem lies too deep for surface techniques to be of any use and when the issue is suspected to lie with an electrical circuit below many layers, destroying the chip can be only way to isolate the fault. We've seen before how certain procedures such as decapsulation require us to crack open the package or casing inside which the sensitive electronics are kept. In today's article, we look at another type of process for which we need to strip or "deprocess" the semiconductor wafer piece by piece. It's called deprocessing.

When performing failure analysis on the defects which can occur in semiconductors, we come across different types of problems each of which needs a separate tool for detection. For example, finding impurities requires us to use light emission spectroscopy methods like Auger spectroscopy. But sometimes the flaw lies in the construction of the chip and not with the materials used.

In such cases, tiny cracks and delaminations between the interfaces must be mapped out without destroying the chip. For this, we use acoustic microscopy which involves sending sound waves through the chip and detecting the way they interact with it.

 

When analyzing the causes of failure on a chip, it’s often useful to obtain high quality close up images of the specimen. Electron microscopy is the technique of choice for this purpose due to its ability to resolve very small images at even nanometer scales. Such images could be used in conjunction with other techniques to present a comprehensive picture of the chip as well as for secondary verification. Scanning electron microscopy services are provided by every failure analysis lab and it’s one of the most important tools we have for identifying errors in a package.